(1) Field of the Invention
The present invention relates to methods for producing integrated circuit devices having lightly doped drain MOSFET with refractory metal polycide gate structures.
(2) Description of Prior Art
The use of polycide gates or interconnect lines, that is a combination of layers of polysilicon and a refractory metal silicide is becoming very important as the industry moves to smaller device geometries. In the past, polysilicon was satisfactory as the gate electrodes and for interconnecting lines. However, as these geometries become smaller, polysilicon has become too high in resistivity for these applications due to its affect on RC time delays and IR voltage drops. The use of a combination of refractory metal silicides with polysilicon has proven suitable because of its lower resistivity.
Silicides of certain refractory metals, i.e. tungsten, molybdenum, titanium, and tantalum have been proven to be suitable for use as a low resistance interconnect material for VLSI integrated circuit fabrication. The disilicides pair very well with heavily doped polysilicon to form polycide gates, because of the criteria of low resistivity and high temperature stability. Tungsten silicide has particularly been found to be capable of overcoming some shortcomings, such as stoichiometry control, surface roughness, adhesion, oxidation and reproducibility to be very useful in combination with polysilicon.
The preferred deposition technique of tungsten silicide is low pressure chemical vapor deposition. The oxidation characteristics of tungsten silicide as produced by this method are very similar to those of polysilicon. The silicon to tungsten ratio in the tungsten silicide film can vary according to the tungsten fluoride and silane gas mixture and reactor conditions. It has been found that low pressure chemical vapor deposited tungsten silicide is stable as soon as the silicon to tungsten ratio is moderately greater than two. Higher silicon concentration is necessary to provide excess silicon during high temperature oxidation, maintain tungsten silicide stoichiometry, and improve silicide adhesion to polysilicon.
It is also a fact that peeling of this polycide film can happen frequently if care is not taken during processing and handling of the wafers. This in turn causes the low yield of the product. This peeling and/or less integrity of the silicide problems are always observed after thermal treatments.
The conventional polycide process forms sequentially the gate oxide layer by thermal oxidation, the polysilicon layer which is then doped, and the refractory metal silicide in situ. These layers are now etched in the desired pattern of polycide gate structures. A silicon dioxide layer is then thermally grown upon the surfaces of the polycide and exposed silicon substrate. The dielectric spacer is formed by blanket chemical vapor deposition of silicon dioxide, a heat densification step and an anisotropic etching of the silicon dioxide layer. The results of this process is peeling of the refractory metal silicide.
The workers in the field have tried to overcome this problem by capping with silicon dioxide during the reaction of titanium with the underlying polysilicon layer such as shown by T. E. Tang et al in U.S. Pat. No. 4,690,730. The peeling was suppressed, but the formation of a noncrystalline layer was found to be inevitable. In addition, the capping layer is detrimental to the source/drain implantation and process control.
Others have tried to overcome this peeling problem by special cleaning steps. For example, wet etchants have been used to clean the polysilicon layer's surface before deposition of the refractory metal silicide. This has resulted in a poor surface and interface between the layers of polysilicon and silicide.
It is therefore an important object of this invention to provide a method for fabricating integrated circuits which overcomes this peeling problem and raises yields.